I assume you mean SystemVerilog transition bins coverage, not FSM transition coverage (which has been supported for years)... This is definitely supported in 8.2. For future reference, if you want to see the docs and "What's New" list for a product without having to install it, you can...
This paper presents several SystemVerilog coding techniques for ensuring a quality transition from a legacy directed test bench to coverage-driven verification and random-test generation. It provides a case study of a SystemVerilog test bench developed for Micron's DDR2 SDRAM chips. Special attention...