License The Basics This repository contains an OpenRISC 1000 compliant processor IP core. The core: Implements a variant of Tomasulo algorithm Supports single and double precision floating point instructions Has
units are unpipelined. You can assume that the latency of the execution stage corresponds to that of the execution unit it uses. Reservation stations and load buffers: Besides load buffers, the processor should have three kinds of reservation stations (see res_station_t data type). Integer rese...