& is used for concatination in VHDL. Cheers Translate 0 Kudos Copy link Reply Altera_Forum Honored Contributor II 10-26-2007 07:11 AM 2,641 Views Yes, but what if n = 1. How do I code it? In meantime i
SignalSlv2was declared using an initial value of all 0’s. Instead of specifying the exact value for each bit, we used(other => '0')in place of the initial value. This is known as anaggregateassignment. The important part is that it will set all bits in the vector to whatever you ...
& is used for concatination in VHDL. Cheers Translate 0 Kudos Copy link Reply Altera_Forum Honored Contributor II 10-26-2007 07:11 AM 2,639 Views Yes, but what if n = 1. How do I code it? In meantime i found i can use following syntax: sync : entity w...