& is used for concatination in VHDL. Cheers Translate 0 Kudos Copy link Reply Altera_Forum Honored Contributor II 10-26-2007 07:11 AM 2,509 Views Yes, but what if n = 1. How do I code it? In meantime i found i can use following syntax: sync...
The std_logic_vector type can be used for creating signal buses in VHDL. It is the array version of the std_logic, the most commonly used type in VHDL.