A TMR Pulse Clocked Flip-Flop for SEU and SET Soft Error Mitigation in Digital CircuitsLawrence Clark
Swept-Frequency Eddy Current Excitation for TMR Array Sensor and Pulse-Compression: feasibility study and quantitative comparison of time and frequency domains processingChaofeng Ye aStefano Laureti bHamed Malekmohammadi cYang Wang aMarco Ricci b
The 12-pulse rectifier is often used to supply high power industrial loads. Its ability to effectively and cheaply mitigate the harmonics on the ac side has ensured its dominance in the industry even as active front ends become cheaper and more reliable. Despite its many benefits, the 12-...
And to assess the heart rate in a contact-free way using a camera [WRS + 12, PMP10, PMP11]. We use linux on arm cortex A se- ries processors . Through the device demonstrates human pulse and heartbeat graph on the display.A. V. Rao...
A unified space vector pulse width modulation (USVPWM) and Alternate inverter pulse width modulation technique for a dual two-level inverter system with two isolated DC voltage sources is used for reducing the total harmonic distortion. The Unified SVPWM can obtain good performance for a wide ...
Basic storage elements are the flip-flops, in this paper we focus on the low power flip-flop using pulse triggered structure based on signal feed through scheme. The proposed pulse triggered flip-flop solves the long discharging path in conventional designs and this design works with the low ...
So here we propose the Pulse triggered Flip-Flop in order to reduce the power Consumption of the circuit. These Pulse Triggered Flip-Flips are designed and analyzed us- ing Tanner T-Spice using TSMC018 Technology.K.SarikaS.Nagi Reddy
This paper analyses the structure of an 12-pulse 7 level voltage source converter (VSC), assembled by combining one twelve- pulse VSC, in conjunction with an asymmetric single-phase seven-level converter plus an injection transformer. The device performance, proven on a lab prototype, allows ...
Pulse Triggered Flip Flop For Low Area and Low PowerA new family of low-power and high-performance flip- flops, namely conditional data mapping flip-flops (CD- MFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We ...
In this paper, a new compensation strategy for receiving clean power of a conventional 18-pulse ac/dc converter formed by three 6-diode bridges is proposed. According to the proposed strategy, a three-phase current-controlled inverter injects the compensation currents into the three positive ...