Sigma Delta (S-D) analog to digital converters (ADC) are central building blocks in modern radio communication systems, and, when studying their performance, it is customary to carry out their analysis in the frequency domain. However, since the frequency-domain is global in nature, one has ...
Table II: SMI’s 2nd generation ADC portfolio Table II shows SMI’s 2nd generation continuous-time delta-sigma ADCs, based on SMI’s revolutionary 2-step SMSP architecture. These ADCs have an order of magnitude wider bandwidth than SMI’s 1st generation ADCs and find applications in high-sp...
Fig. 3. Pixel intensities and results of the TDA-ADC: (a) pixel intensities and (b) its results. Fig. 4. Structure of the TDA-ADC. delay circuits, latched sense amplifiers (SAs) for a timing memory, and a pixel value encoder. The TDA-ADC employs the speed of decreasing voltages at...
Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.Keywords: Skipping-window technique; DAC ...
Time-domain Measurement and Calibration of Mismatch Errors in Multi-chip ADC Time-interleaved Systems 多片ADC并行采集系统的误差时域测量与校正 www.ilib.cn 4. Time-domain Measurement of Permittivity of Concrete Materials by Wavelet Modeling 小波建模法在混凝土材料介电常数时域测量中的应用研究 service.ilib...
Therefore, the ADC bandwidth is reduced which may increase the signal to noise and distortion ratio and the effective number of bits, as investigated for sinc-pulse sequences in Ref.24. Discussion We have presented a method for the very simple recursive generation, multiplexing and demultiplexing ...
In this paper an advanced ultra-fast broadband time-domain EMI (TDEMI) measurement system based on a multi-level analog-to-digital converter (ADC) is presented. The proposed multi-level quantization system is compared with a single ADC system. The multi-level system is modelled and investigated...
A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS Hsieh, "A 0.4V 2.02fJ/conversion-step 10- bit hybrid SAR ADC with time-domain quantizer in 90 nm CMOS," in Proceedings of the Symposium on VLSI ... Chen,Yan-Jiun,Hsieh,... ...
(16-bit ADC, advanced calibration features) Industry's most accurate cable length measurements (25 μm [0.76 ps] cursor resolution) Industry's fastest intermittent fault detection (250,000 samples per second, 500 Hz continuous full waveform capture) Industry's only portable TDR exceeding all Tektr...
This paper presents a 0.5-V 12-bit low-voltage power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) using an adaptive time-domain (ATD) comparator with noise optimization. To be power efficient with different residual input levels (n$Delta V_{mathrm {in}}$...