Analog-binary CCD correlator: a VLSI signal processor -gate tap structure minimizes code-dependent bias, harmonic distortion, and tap-to-tap nonuniformity, while holding power dissipation to 1 mW per tap. ... Gandolfo,A D.,Tower,... - Solid-State Circuits, IEEE Journal of 被引量: 29发表...
Efficient VLSI architectures for high-speed Ethernet transceivers. such as 10 Gigabit Ethernet over copper (10GBASE-T), with the goal to reduce the hardware complexity and power consumption of various DSP components whil... J Chen - University of Minnesota. 被引量: 0发表: 2008年 Method For ...
Error-free VLSI architecture for the 2-D Daubechies 4-tap filter using algebraic integers In this paper, a multi-encoding approach using wavelet based subband coding is proposed to accomplish error free calculations from exact representation of ... S Madishetty,A Madanayake,RJ Cintra,... - IEE...
4.The system of claim 1 wherein the test bench file comprises vectors that write values in registers of the port so as to set the respective cell into a defined state. 5.The system of claim 1 wherein the output file is further operative to deliver the simulation data to the test progra...
MIDRANGE VLSI HEWLETT-PACKARD PRECISION ARCHITECTURE COMPUTER The goal established for HP Precision Architecture computers was to provide a scalable set of hardware and software with the flexibility to be configured for many different applications in a wide variety of market areas. The HP 9000 Mode.....