Hi, yes I saw the same things on Stratix IV. The problem is the PCIE macro that at the moment has not the code in vhdl. The only solution is to
module D_flipflop( <Error (10500): VHDL syntax error at VarilogHDLcodeTrial1.vhd(5) > It asks for"is" then after that asks for "of" Clock, Set, Reset, LEDA, LEDB, LEDC, LEDD, LEDE ); input wire Clock; input wire Set; in...
Unfortunately the PCIe based system isn't working so I want to simulate it to see what's happening, but Qsys is erroring on testbanch generation because my application is written in VHDL. Has anyone else seen this problem? Is there a way round it? Thanks for any p...