One of the features not supported by Quartus is the general unconstrained type, although Quartus supports unconstrained arrays. Interestingly enough, many of the features of system verilog have been implemented
1. Open Quartus and create a project (if not existing yet) 2. Open the TCL shell in Quartus  3. Execute the command `source <open-logic-root>/tools/quartus/import_sources.tcl` Replace `<open-logic-root>` by the path of your *Open...
Yes, the top-level port feature that you want can be done by Pro version hw.tcl SystemVerilog interface command. I had checked internally that this feature only be implemented starting from Pro version 17.1. That's why you'll see package require -exact qsys 17.1 ...
The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal. It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary out...
As tool support for this sort of thing tends to be based on user demand, I'd just like to chime in and say that I'd definitely like to see case inside as a feature supported for synthesis in the future. The coding work-arounds to effectively implement this function...
One of the features not supported by Quartus is the general unconstrained type, although Quartus supports unconstrained arrays. Interestingly enough, many of the features of system verilog have been implemented by Quartus . . . which got me looking into the lanugage. In my career, I have ...