PURPOSE:To eliminate the need of extending a different bus between other modules by constituting the system so that in the case a microprocessor reads out data from a memory, a bus can be allocated to other module after sending out an address to the bus. CONSTITUTION:A system bus controller...
摘要: 介绍一种用于微处理器系统的高性能背板总线.这种并行总线支持32位非多路复用地址和数据高速公路上的单块和块传输周期.传输由异步握手协议控制.总线分配提供了多处理器体系结构.该总线还支持模块间中断,以促进对内部和外部事件的快速响应.电路板和机箱的结构基于IEC 60297. 注:1.该总线与VME总线类似. 2.关于...
A microprocessor system, including a central processing unit (CPU), data source device and data destination device electrically interconnected by first data bus lines, address bus lines and control bus lines of a system bus, is implemented with a transfer signal control line, and second data bus...
United States Patent US4514799 Note: If you have problems viewing the PDF, please make sure you have the latest version of Adobe Acrobat. Back to full textHome Search Services Contact us © 2004-2024 FreePatentsOnline.com. All rights reserved. Privacy Policy & Terms of Use....
such as a PCI bus. The interrupt sources also include devices coupled to a second peripheral bus, such as an ISA bus. The central interrupt control unit is operative in two modes. In a first mode, referred to as a pass through mode, interrupts from ISA peripheral devices are provided ...
PURPOSE:To reduce the load of extension on software and improve the extendability of a system by converting system bus imformation between a microprocessor-applied device body and an additional device into serial data, and transferring the data. CONSTITUTION:When a CPU drives data information and a...
A universal serial bus (USB) memory system and a control method thereof are disclosed. The USB memory system includes a microprocessor, a storage unit in communication with the microprocessor, an interface unit in communication with the ... CL Wang,KS Pua,TH Kuang - US 被引量: 136发表: 20...
System and method for reducing memory latency associated with a bus microprocessor systems a system and method for signaling a delayed response to a Datenanaforderung in a connected to a bus system, there have been described. In one embodiment, a... JD Gilbert,HD Joyce,B Ramamoorthy,... ...
of plural times. CONSTITUTION:In case of write operation, by the first write command, an output (ADR/DAT7-0) of a microprocessor (muCPU)1 passes through a bidirec tional drive 5 and it is written on a memory I/O11 and a memory I/O which has been connected to a system bus. By ...
PROBLEM TO BE SOLVED: To provide a microprocessor which has the degree of freedom to the acquisition and release of a bus right which are performed by handshake. ;SOLUTION: When a microprocessor 1 is assigned to a master processor in a multiprocessor system, and when bus right release permissi...