AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication - tinyloop/axi
The circuit is designed using standard library cells only and is described in Verilog HDL. This enables design automation and simplifies the design of digital signal processing circuits for modern System-on-a-Chip.Rustam Khalirbaginov会议论文
Verilog codeUltra-low power designThis article presents a fully-synthesizable digital voltage regulator for applications with extremely low power consumption. The proposed design uses a synthesizable controller (DLDOC) to detect load fluctuations and control a tri-loop structural design. This tri-loop ...
In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational trans...