The source and sink landscape patterns refer to landscape types or units that can either promote positive evolvement of non-point source(NPS) pollution pro... JL Wang,NI Jiu-Pai,CL Chen,... - 《山地科学学报(英文版)》 被引量: 1发表: 2018年 High-voltage semiconductor devices having buried...
For applications that require more power, the regulator must be mounted separately on a heat sink to dissipate the heat. In all-surface-mount systems, this is not an option, so the limitation of power dissipation (1W for example) limits the output current. Unfortunately, it is not easy to ...
The load determines the sink time constant, influencing phase performance and overall stability. The LT1070's internals have been designed with all this in mind and compensation is usually fairly simple. In this case the 1k to 1µF combination at the compensation pin (VC) rolls off the ...
When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less ...
The 32-Gbps Fibre Channel switching module also provides existing features such as predictable performance, high availability, advanced traffic management capabilities, integrated VSAN and IVR, resilient high-performance ISLs, hardware-assisted slow-drain support, comprehensive secur...
Each switch-on and switch-off event occurs during a defined period of time, in which the device state changes from blocking to conducting and vice-versa. The time required for these switching operations depends on the device gate charge characteristics ...
Drain Current4.5A 源漏极导通电阻Rds Drain-Source On-State Resistance0.8Ω~1.0Ω (VGS = 10 V, ID = 2.5 A) 开启电压Vgs(th) Gate-Source Threshold VoltageVth = 1.5 to 3.5 V (VDS = 10 V, ID = 1 mA) 耗散功率Pd Power Dissipation20W ...
Figure 20 shows the same waveforms with the load in- creased to 2mA. Loop oscillation frequency increases to keep up with the load's sink current demand. Now, the VC pin waveform (Trace D) begins to take on a filtered ap- pearance. This is due to R1-C1's 10ms time constant. If...
B. Heatsink Requirements: An estimate of the worst case power dissipation of the power switch and output catch diode can be made over line and load ranges. C. Control Circuit: The UC3861-64 series of controllers will be examined and pro- grammed per the design requirements. Programming the...
While this IC was originally designed to be dual clock driver for MOS logic it was capable of supplying up to 1.5 amps as either a source or sink. In addition, it was made with a gold doped, all NPN process which minimizes storage delays, and as a result, offers transition times of ...