如上图,这种Stuck open可以用两组Stuck At的向量进行测试,AB输入从10变换到00,可以检测出这种Stuck Open的fault,也就是说大部分的Stuck Open/Short的faults都是可以通过Stuck At model的测试向量覆盖的。 这种通过向量(function)的方式来测试Stuck Open/short,可能需要非常多的测试图形,需要的测试时间和成本都很多。...
2.Based on the analysis and research on FAN algorithm, an IDDT test pattern generation algorithm for stuck-open faults is p.本文采用启发式搜索的方法,基于对FAN算法的分析,在不考虑冒险的情况下对于CMOS电路中的开路故障,探讨了利用FAN算法进行瞬态电流测试生成的可能性。 英文短句/例句 1.REPAIR THE OPE...
In the proposed method, although the stuck-open faults are treated at switch level in each cell consisting of CMOS logic gates, test patterns for the overall circuit are generated at gate level using a path sensitization method. To reduce the number of test patterns, a gate level circuit is...
The design admits a universal test sequence TS that robustly detects all single stuck-open faults in the CMOS transistors. For an n-variable switching function, TS consists of only (2n + 8) vectors and can be generated by a simple test pattern generator. All single stuck-at faults in the...
In this direction, a new hierarchical test generation methodology for transistor stuck-open (TSOP) faults in combinational CMOS circuits, is presented. The contribution of this work is twofold. For the designer of the CMOS cells we give a method, based on the Karnaugh map, to generate the ...
While most of the fault diagnosis tools are based on gate level fault models, many faults are actually at the transistor level. The stuck-open fault is one of them. In this paper we introduce a stuck-open fault diagnosis method based on the stuck-at fault model. First we investigate how...
However, it is difficult to generate robust test patterns and they may not exist for some stuck-open faults. In this paper, to overcome this difficulty, we propose a new testable design method with the robustness. Since a faulty gate is regarded as a tri-state element, the gate output ...
A design method for a 2-rail logic combinational circuit is proposed, where stuck-open and stuck-on faults in FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, OR and AND, are also adde...
On the Chambers-Mallows-Stuck method for simulating skewed stable random variables Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits...
An Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuits In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, called SOPRANO, in CMOS combinational circuits... HK Lee,DS Ha - 《Vlsi Design》 被引量:...