ball side 8 7 6 5 4 3 2 1 A VDD_3 VSS_3 BOOT0 PB5 PB3 PD2 PC10 VDD_2 BYPASS/ B PC14 PC15 PB9 PB6 PB4 PC11 PA14 V SS_2 C PC13 NRST V PB7 PC12 PA15 PA12 PA11 BAT D OSC_IN OSC_OUT PC2 PB8 PA13 PA10 PA9 PC9 E PC0 V PA1 PA5 PA8 PC8 PC7 PC6 SSA PA...
deep sleep mode的进入要等到APB相关操作完成才会延迟进入。 使用示例:通过RCC寄存器配置Clock的代码stm在system_stm32f0xx.c中提供,涉及的函数为SystemInit和SystemCoreClockUpdate。 在reset后,cortex m0 core默认使用8M HSI作为系统时钟源,接着会在SystemInit()函数中配置要使用的系统时钟。因为使用的stm32f0308-disco...
STM32F103xC/D/E performance line WLCSP64 ballout, ball side 87654321 A VDD_3 VSS_3 BOOT0 PB5 PB3 PD2 PC10 VDD_2 B PC14 PC15 PB9 PB6 PB4 PC11 PA14 BYPASS/ VSS_2 C PC13 NRST VBAT PB7 PC12 PA15 PA12 PA11 D OSC_IN OSC_OUT PC2 PB8 PA13 PA10 PA9 PC9 E PC0 VSSA PA1...
Pinouts and pin descriptions STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side 8 7 6 5 4 3 2 1 A VDD_3 VSS_3 BOOT0 PB5 PB3 PD2 PC10 VDD_2 B PC14 PC15 PB9 PB6 PB4 PC11 PA14 BYPASS/ VSS_2 C PC13 NRST VBAT PB7 PC12 PA15 PA12 PA11 D OSC_IN OSC_...
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 36/143 DS5792 Rev 13 STM32F103xC, STM32F103...
• Flash prefetch on • Flash memory timing set to 2 wait states • FLITF clock stopped in Sleep mode Workaround When using the flash memory with two wait states and prefetch on, the FLITF clock must not be stopped during the Sleep mode – the FLITFEN bit in the RCC_AHBENR r...
STM32F103xC/D/E performance line WLCSP64 ballout, ball side 87654321 A VDD_3 VSS_3 BOOT0 PB5 PB3 PD2 PC10 VDD_2 B PC14 PC15 PB9 PB6 PB4 PC11 PA14 BYPASS/ VSS_2 C PC13 NRST VBAT PB7 PC12 PA15 PA12 PA11 D OSC_IN OSC_OUT PC2 PB8 PA13 PA10 PA9 PC9 E PC0 VSSA PA1...
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied ...
STM32F103RD STM32F103VD STM32F103ZD STM32F103xE STM32F103RE STM32F103ZE STM32F103VE LQFP64 10 × 10 mm, LQFP100 14 × 14 mm, LQFP144 20 × 20 mm LFBGA100 10 × 10 mm LFBGA144 10 × 10 mm WLCSP64 www.st.com Contents STM32F103xC, STM32F103xD, STM32F103xE 2/143 DS5792 Rev 13 Con...
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 36/143 DS5792 Rev 13 STM32F103xC, STM32F103...