testbench.sv 1 module jsrflipfloptb; 2 wire q, qbar; 3 reg clk,rst; 4 reg [1:0] sr; 5 6 jsrflipflop jsrff(q,qbar,clk,rst,sr); 7 always #5 clk = ~clk; 8 9 initial 10 begin 11 clk = 1'b0; 12 rst = 1; # 10; rst = 0; #10; 13 $display("RSLT\...