As dr2 is equal to 0, the logic can be simplified. The carry output of the full adder 408 is input to one gate of an exclusive OR gate 412. The exclusive OR gate 412 also receives from an inverter 413 the inverted value of r1. As dr1 is equal to 1, the logic can again be ...
As dr2 is equal to 0, the logic can be simplified. The carry output of the full adder 408 is input to one gate of an exclusive OR gate 412. The exclusive OR gate 412 also receives from an inverter 413 the inverted value of r1. As dr1 is equal to 1, the logic can again be ...
The simplified operation requires three and four clock cycles of latency for each boundary cell and internal cell, respectively. Unlike the first systolic array for performing triangularization and back-substitution, this array does not require any feedback loop. Thus, it is easier to operate this...
The SRT algorithm has been extended to square root calculations allowing the utilization of existing division hardware. The simplified square root equation looks surprisingly similar to that of division. See, M. D. Ercegovac and T. Lang, "Radix-4 square root without initial PLA," IEEE Trans. ...