All parts expect the SPLL to run at 702MHz. In U-Boot it's the SPLL_HZ declaring this rate and in the kernel it's a fixed clock definition. While everything is expecting 702MHz, the SPLL is not running that fre
return rk3588_scru_clk_get_rate(clk); } +static int rk3588_scru_clk_probe(struct udevice *dev) +{ + int ret; + + ret = rockchip_pll_set_rate(&rk3588_pll_clks[SPLL], + (void *)SBUSCRU_BASE, SPLL, SPLL_HZ); + if (ret) + debug("%s setting spll rate failed %d\n",...
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davinci_venc davinci_venc: Desired VENC clock not available davinci_venc davinci_venc: PLL's doesnot yield required VENC clk 请问什么原因,我在dm368平台上移植dvsdk4.02.。并播放编码后的264文件,视频播放图像比较快,不是很平滑的视频图像,但感觉好像没丢帧。
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When I open up mysdc.sdc, I did not get individual create_gen_clk commands in the sdc file, instead what I get is only the command "derive_pll_clocks" in the sdc. Is my step incorrect or is the QII handbook not right (the quote above)? Can some kind souls point me ...
I'm trying to use the LVDS CCM_CLK1_P and CCM_CLK1_N pins to drive the internal PLL's on my imxrt1062 chip. When I use the 24 MHz external crystal oscillator, I can setup my ARM PLL at 528 MHz and the rest of the system at my desired frequencies. However, I'm unable...
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但是他说遇到报错:Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). 其实这是因为 普通IO 没有wire到 PLL,需要先用 CLKCTRL IP 将普通IO 连上 全局时钟等,然后再进PLL,这样就不会有这样的报错了。
Can some kind souls point me to how I can get individual create_gen_clk commands? (the reason I want the individual gen_clk is because I need the exact name of the pll inclk port and the pll outclk port) Thank you. Translate0...