Question 1: In the datasheet section 2.1 you can read that slew rate disabled and normal drive strength, what is the meaning of disabled (fast or slow) and normal (high or low) ? Question 2: I'am using PTD1 pin as SPI clock line. The drive strength enable control can not be change...
I am running a 9s12xhz512 with a serial chain attached to the SPI. If SRRS bit 6 (SCLK) is set to limit the slew rate of this pin then data always comes back as zero. I can monitor the data at the MISO pin and see the data is clearly both high and low...
Adjustable slew rate at 2 levels Internal charge pump Half-bridge independent mode Current sense for high side and low side On-state open load detection SPI interface Watchdog 优势 Small package with very low pin count No need for external capacitors Costs savings Enhanced t...
1.62 V to 5.5 V • Factory-calibrated – NIST traceability • Low power consumption • Programmable temperature alert limits • Temperature slew rate warning • Optional Cyclic Redundancy Check (CRC) • 3-wire SPI interface 2 Applications • Wireless communication equipment • Field trans...
Adjustable slew rate at 2 levels Internal charge pump Half-bridge independent mode Current sense and error flag pin Current sense for high side and low side On-state open load detection SPI interface 优势 Small package with very low pin count ...
Adjustable slew rate at 2 levels Internal charge pump Half-bridge independent mode Current sense and error flag pin Current sense for high side and low side On-state open load detection SPI interface Vorteile Small package with very low pin count No need for external capaci...
AEC-Q100 qualified (Grade 1) Adjustable slew rate at 2 levels Internal charge pump Half-bridge independent mode Current sense and error flag pin Current sense for high side and low side On-state open load detection SPI interface Benefits ...