Low Density Parity Check used in VLSI Implementation of FPGAs for Soft-Error Resilient Circuits Providing Optimal CircuitsV. J. Beulah Sherin PonmalarM. Ruth JenilaESRSA Publications
G. in 2014 Symposium on VLSI Circuits Digest of Technical Papers (IEEE, 2014). Biggs, J. et al. A natively flexible 32-bit Arm microprocessor. Nature 595, 532–536 (2021). Article CAS Google Scholar Wang, S. et al. Skin electronics from scalable fabrication of an intrinsically ...
In Section 2, the MIMO system model is introduced and the employed hard-output and soft-output STS- SD algorithms are reviewed. In Section 3, we develop a receiver architecture suitable for wide-band MIMO systems and analyze the optimization goals for the SD-core implementations. The VLSI ...
Based on this consideration, it is proposed to use a cache smaller than the RF to store the ECC of physical registers and replace check bits of “short-lived” registers with those of the “long-lived” ones. 3.4.2. Propagation to specific signals at the service interface The AVF ...
a随着VLSI规模和复杂程度的不断提高,以可复用IP核为代表的软模块在VLSI设计中得到广泛应用 Along with the VLSI scale and the complex degree unceasing enhancement, obtain the widespread application take may the multiplying IP nucleus as representative's soft module in the VLSI design[translate]...
Radiation-induced soft errors in advanced semiconductor technologies IEEE Trans. Device Mater. Reliab. (2005) D. Bol et al. Interests and limitations of technology scaling for subthreshold logic IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2009) S. Lin et al. Analysis and de...
A new physical mechanism for soft errors in dynamic memories Guillaume HubertL.A. et al. Impact of scaling on the soft error sensitivity of bulk, fdsoi and finfet technologies due to atmospheric radiation Integr., VLSI J. (2005) ManoochehriM. et al. CPPC: Correctable parity protected ...
A Jagirdar,R Oliveira,TJ Chakraborty - International Conference on Vlsi Design 被引量: 14发表: 2008年 SOFT ERROR CORRECTING METHOD PURPOSE:To improve reliability for a device without affecting on memory capacity and cost by correcting an error by the result of performing vertical parity check and...
VLSI Design and Test for Systems Dependability 1504Accesses Abstract We will begin by a quick but thorough look at the effects of fault s, error s and failure s, caused by terrestrial neutron s originating from cosmic rays , on the terrestrial electronic systems in the variety of industries. ...
on VLSI Design, Coeur d'Alene, Idaho, USA, Oct. 4-5, 2005. P. S. Bottorff et al., “Test Generation for Large Logic Networks,” in Proc. of the 14th Design Automation Conf., Jun. 1977, pp. 479-485. P. K. Lala, “Self-Checking and Fault-Tolerant Digital Design,” Morgan ...