| SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);if(ret <0)returnret;/* Set the AP DAI configuration */ret =snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);if(ret <0)returnret;/* Set WM8580 to drive MCLK from its PLL...
*/staticintcs4270_set_dai_fmt(struct snd_soc_dai *codec_dai,unsignedintformat){structsnd_soc_component*component=codec_dai->component;structcs4270_private*cs4270=snd_soc_component_get_drvdata(component);/* set DAI format */switch(format & SND_SOC_DAIFMT_FORMAT_MASK) {caseSND_SOC_DAIFMT_I2...
McASP’s transmit and receive clocking sections are intended to operate synchronously (ASYNC=0), codec is clock and frame master (SND_SOC_DAIFMT_CBM_CFM). The problem is that with the davinci-mcasp driver implementation provided with SDK 06.03 (4.19.94-gbe5389fd85) the RX secеion is ...
SAI_XFRCR_FSDEF;/* DAI clock strobing. Invert setting previously set */switch(fmt & SND_SOC_DAIFMT_INV_MASK) {caseSND_SOC_DAIFMT_NB_NF:break;caseSND_SOC_DAIFMT_IB_NF: cr1 ^= SAI_XCR1_CKSTR;break;caseSND_SOC_DAIFMT_NB_IF: frcr ^= SAI_XFRCR_FSPOL;break;caseSND_SOC_DAIFMT_IB_...
err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | \ SND_SOC_DAIFMT_NB_NF | \ SND_SOC_DAIFMT_CBS_CFS);if(err <0) { printk(KERN_ERR"cpu_dai fmt not set \n");returnerr; } err = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_MCLK1, ...
pr_debug("24bit or 32bit\n");switch(sta32x->format) {caseSND_SOC_DAIFMT_I2S: confb |=0x0;break;caseSND_SOC_DAIFMT_LEFT_J: confb |=0x1;break;caseSND_SOC_DAIFMT_RIGHT_J: confb |=0x2;break; }break;case20: pr_debug("20bit\n");switch(sta32x->format) {caseSND_SOC_DAIFMT_I2S...
SND_SOC_DAIFMT_CBS_CFS);if(ret <0)returnret;/* set cpu DAI configuration */ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);if(ret <0)returnret;/* set the codec system clock for DAC and ADC */ret = snd_soc_dai_se...