20150213179LEAKAGE POWER REDUCTION IN INTEGRATED CIRCUITS BY SELECTIVE REMOVAL AND/OR SIZING OF SWITCH CELLSJuly, 2015Dangat et al. Primary Examiner: SIEK, VUTHE Attorney, Agent or Firm: Seed IP Law Group LLP/STMicroelectronics (SEATTLE, WASHINGTON, US) ...
Shibasaki, et al., “A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS”, IEEE 2014 Symposium on VLSI Circuits Digest of Technical Papers, 2 pgs. Hidaka, et al., “A 4-Channel 125-10.3 Gb/s Backplane Transceiver Macro With35 dB Equalizer and Sign-Based Zero...
The utility of deliberate skews for optimizing the performance of VLSI circuits has been demonstrated, and algorithms for performing skew scheduling and period minimization have been presented. Deliberate skews can also be used in conjunction with other timing optimization strategies and for minimizing the...
D. GuerreroM. BellidoJ. JuanA. MillanP. RuizE. OstuaJ. ViejoGroup of Digital Design, Microelectronic Institute of Seville -CNM & Dep. of Electronic Technology, University of SevilleVLSI Circuits and Systems II pt.1
In Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, The Netherlands, 1–3 October 2014; pp. 222–227. [Google Scholar] Shi, C.; Sánchez-Sinencio, E. An On-Chip Built-in Linearity Estimation Methodology ...