Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithmsdoi:10.1016/j.vlsi.2017.08.003Kunwar SinghAman JainA. MittalVinayak YadavA. SinghA. K. JainManeesha GuptaElsevierIntegr.
Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumptio... R Vaddi,S Dasgupta,...
Automatic transistor sizing in high performance CMOS logic circuits The authors present new methods for optimization-based automatic transistor sizing in digital CMOS VLSI circuits. The main novelty of their approach is tha... B Hoppe,G Neuendorf,D Schmittlandsiede - Compeuro 89, Vlsi & Computer...
Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction This brief presents an improved logical-effort model to account for the slope mismatch between the input and output of a gate. The model has a simple formu... Wang, C.C.,D Markovic - 《IEEE Transactions ...
关键词: CMOS logic circuits Monte Carlo methods circuit simulation integrated circuit modelling integrated circuit reliability Monte Carlo simulation circuit simulation circuit variability delay penalty domino keeper sizing 会议名称: Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium...
In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing in order to guarantee synchronously arriving signal slopes at the input of logic gates. Since the delay of a logic gate depends directly on transistor sizes, the variation of channel-widths and -...
bufferpositioningandsiz—ing,.Buffersizesarediscreteintegersratherthancon—tinuousvariables.ComparedwithRef.11]-I3],buffersizingwasalreadvdiscussedinRef.[5]andl6J,butitwasassumedascontinuousinRef.[5];whilethealgo—rithmproposedinRef.16]canonlybeappliedto吼(PassTransistorLogic)circuits.BasedonCMOS...
In this article, we will learn how to find the optimal size of a transistor/logic gate present in a larger circuit to provide the desired performance using the linear delay model. In this continuation of our series on transistor sizing in VLSI, we'll go over the third and final model ...
9. A semiconductor die having adaptive keeper logic, comprising: a plurality of dynamic circuits, each dynamic circuit including an adaptive keeper circuit capable of being adjusted based on a bit code; a process corner databank having process corner data that indicates a process corner of the se...
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