RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100 - Layheng-Hok/RISC-V-CPU
Developed all components in Verilog, adhering to the RISC-V architecture specification. Designed a top module integrating all submodules into a cohesive processor. Implemented a testbench for simulation to verify the correct execution of instructions and control flow. Organized the memory to handle var...
Code README MIT license Single-Cycle CPU This project is a simple verilog project to implement a single-cycle CPU. The CPU is based on the 32-bit MIPS instruction set under Harvard architecture. The CPU is designed to be able to run on FPGA board. ...
Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier. Topics mips mips-assembly verilog computer-architecture mips-architecture single-cycle multi-cycle booth-multiplier single-cycle-processor multi-cycle-processor Resources Readme License MIT license Activity Stars 0 stars Wa...
x31 as well as RDCYCLE[H], RDTIME[H], and RDINSTRET[H] instructions, turning the processor into an RV32E core. Furthermore it is possible to choose between a dual-port and a single-port register file implementation. The former provides better performance while the latter results in a ...
Lab3: Construct a single-cycle CPU with Chisel License MIT license 0 stars 51 forks Branches Tags Activity Star Notifications huaxinliao/ca2023-lab3 main BranchesTags Code Folders and files Latest commit History12 Commits csrc project src test_run_dir verilog/verilator .clang-for...
Verilog implementation of a computer architecture project (single-bus processor) on an iCEstick FPGA Initial Writeup In our computer architecture class, we were tasked with a project which involved developing a gate-level design of a single-bus control unit that implements 16 different instructions ...
通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器 - zach0zhang/Single_instruction_cycle_OpenMIPS
Code Folders and files Latest commit History11 Commits img vsrc README.md verilated_cpu.cpp Repository files navigation README 开岁—— 一个简单的 7 级流水标量乱序 RISC-V 核 这个仓库是作者的本科毕业设计,支持 RV64IM 指令集和常规计算指令(单周期 ALU 指令和多周期乘除指令)的乱序执行(但无...
Single instruction processor and toolchain. Contribute to suyashmahar/urisc development by creating an account on GitHub.