I have a couple of Quartus II Verilog standard compliance related bug reports of which this is the first one. If this is not the right place to report bugs: please point me in the right direction.. Consider the following test case: module issue_001(a, b, y); input ...
I have a couple of Quartus II Verilog standard compliance related bug reports of which this is the first one. If this is not the right place to report bugs: please point me in the right direction.. Consider the following test case: module issue_001(a, b, y); input a; input b...