-- FYI: Same Code not using Shift Operator: Input_Delay(1) <= Input_Delay(0); Input_Delay(2) <= Input_Delay(1); Input_Delay(3) <= Input_Delay(2); Input_Delay(0) <= Input; ifInput_Delay(3) ='1'then -- Do Stuff
We can also implement the shift register in Verilog, with the listing as shown here: 1 module shift_register ( 2 clk , // clock input 3 rst , // reset ( active low ) 4 din , // Digital Input 5 shiftreg // shift register 6 ); 7 8 input clk; 9 input rst; 10 input din; ...
Input_Delay(0) <= Input; -- FYI: Same Code not using Shift Operator: Input_Delay(1) <= Input_Delay(0); Input_Delay(2) <= Input_Delay(1); Input_Delay(3) <= Input_Delay(2); Input_Delay(0) <= Input; if Input_Delay(3) = '1' then -- Do StuffLearn...