Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuitsimplemented in state-of-the-art CMOS technology. A pre-requisite for employing SSTA is the characterizationof the setup and hold times of the latches and flip-flops in the cell library. ...
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basic building blocks, called “cells”, which represent logic (e.g., a NAND gate), and memory (e.g., a flip-flop). Timing considerations are paramount when designing complex circuits such as very large-scale integrated (“VLSI”) circuits, which can be formed of many millions of cells...
Accordingly, it is desirable to develop a bus receiver which minimizes the pull-up time of the PFETs and the setup time of the latching circuit while also decreasing power dissipation per unit of chip area in a VLSI implementation of the bus receiver. The CMOS bus receiver and inverter circu...
Field of the Invention The present invention relates to a setup / hold time control circuit. In particular, in a VLSI chip structure that receives a signal from an external source, the external input signal and the input register of the VLSI chip use different clocks. Disclosed is a ...
Field of the Invention The present invention relates to a setup / hold time control circuit, and in particular, metastability of a signal transmitted when connecting registers using different clocks in a VLSI chip structure using multiple clocks. Disclosed are techniques for preventing the phenomenon....
After that, we propose an ILP formulation and show the experimental results for some benchmark circuits.Keisuke INOUEMineo KANEKOTsuyoshi IWAGAKI電子情報通信学会技術研究報告. VLSI設計技術. VLSI Design Technologies