The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}′. These signals have rising and falling transistors with the same delays for the Q signal and the {...
The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}′. These signals have rising and falling transistors with the same delays for the Q signal and the {...