Without looking at your design, if these clock domains are asynchronous, you should use set_clock_groups to simply cut all paths between them. By using set_max[min]_delay, the tool will still analyze timing on paths that go between these clock domains and you see what's...
Hi sir, I face one problem, and I have no idea for the set_max_delay and set_min_delay constrains, the problem as follows: I want to constrains the
当飞行员接收到上传的CPDLC信息“SET MAX UPLINK DELAY VALUETO [XX] SECONDS ”时。1、无论飞机是否具有延迟监视功能,根据飞机设备的提示,飞行员应积极回应ATC,如使用ACCEPT或者ROGER。 飞行员必须对“SET MAX UPLINK DELAY VALUE TO [XX] SECONDS”信息做出响应,以避免在系统中打开未应答的CPDLC信息。这也适用...
The electronic max. value monitoring device has adjustable waiting time and is controlled by pulses of a pulse counter proportional to the energy consumption. A time-base circuit generates the nominal values. Its response value is adjustable and its output delivers signals when maxima are exceeded....
飞行员必须对“SET MAX UPLINK DELAY VALUE TO [XX] SECONDS”信息做出响应,以避免在系统中打开未应答的CPDLC信息。这也适用于信息延迟监视功能不足或没有此类功能的飞机。 《全球数据链接操作手册》规定,当飞机上没有信息延迟监控功能时,飞行员应修改下传信息“TIMER NOT AVAILABLE”发送给ATC。
I have tried to do it like this, created a virtual clock of 160MHz and set_input_delay w.r.t to virtual clock but it gives timing failure with reference to PLL generated clock 2- One of the input signals is an I/O signal and also asynchronous (coming from a micro-controller) how...