This paper presents a new reseeding technique that reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed ...
Improving diagnostic test coverage from detection test set for logic circuitsThe proposed work aims at generating a diagnostic test set which is a compact test set derived from a large set of test vectors generated from any automatic test pattern generator (ATPG). This diagnostic test set is ...
Ord is the test patterns generated by the ATPG (automatic test pattern generation) tool of Atalanta [20] before using the proposed scheme, and Pro is the new test patterns with new orders that under the proposed optimized schemes. Because the proposed scheme reordered test patterns which made ...
Advancement in Onchip Clocking to Improve ATPG Coverage Between Clock Domains Things are not tough when we have to deal with flops driven with same clock domain. However, achieving good test coverage for TDF fault model when flops are driven by two different clock domain is a challenge. This ...
S.K. Kumar, S. Kundu, S. Chattopadhyay, Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing, Integr., VLSI J. 45 (2) (2012) 211-221.KrishnaKumar, S., N. Subhadip Kundu, Santanu Chattopadhyay, 2012. "Customizing completely specified pattern...
We could achieve an average reduction of 84.78% in dynamic power and 6.52% in leakage power for pattern set generated by the ATPG tool Atalanta. Similar savings could also be achieved on test set generated by the commercial ATPG tool Tetramax.S. Krishna Kumar and Subhadip Kundu and Santanu ...
The proposed constant test set is much smaller than ATPG generated or algorithmic test set, resulting in low power testability. As the GF(2{sup}m) multipliers have found some critical field applications and need for efficient online testing, Built-in Self-Test (BIST) circuit is proposed to ...
This paper presents a new reseeding technique that reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed ...
We show that complete fault coverage of all leakage faults is possible using relatively small binaries with low latency to fault detection and by utilizing only a few strategically placed counters in the μP. Keywords: fault emulation; RISC-V; FPGA; ATPG; fault analysis; fault detection; DFT;...
RISC-VFPGAATPGfault analysisfault detectionDFTinformation leakagecryptographySOFTWARERecent evaluations of counter-based periodic testing strategies for fault detection in Microprocessor (mu P) have shown that only a small set of counters is needed to provide complete coverage of severe faults. Severe ...