SLAS516C – DECEMBER 2006 – REVISED JULY 2009 LOW-POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE FEATURES 1 •2 2.7-V to 5.5-V Analog Supply, Low Power: – 15.5 mW (1 MHz, +VA = 3 V, +VBD = 1.8 V) • 1-MHz Sampling...
Power supply Power supply input to the device. No connect The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. The EXPOSED PAD should not be soldered on the PCB. Note 1. SI may be connected to SO for a single pin data interface. Document Nu...
The latch enable input must be high for at least one clock cycle before going low, and then must be held low for at least one clock cycle. The last 16 data bits clocked into the serial input register are the ones that are transferred to the DAC input register when latch enable goes ...
3.3 Serial clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial data input (D) are latched on the rising edge of Serial clock (C). Data on Serial data output (Q) change fr...
3.3 Serial clock (C) This is a CMOS input with no internal pull up/down. This signal synchronizes the timing of the serial interface. The instructions, the addresses, or the data present on the serial data input (D) are latched on the rising edge of the serial clock (C), while the...
Latch bit, it is only valid for the Write Status Registers instruction to change the volatile Status Register bit values (After the software reset or re-powered, the volatile Status Register bit values will be restored to the default value or the value input by the Write Enable instruction)....
In a shift register, this corresponds to the "latch" input, which transfers the received data to the output lines. Multiple Peripherals There are two ways of connecting multiple peripherals to an SPI bus: 1. In general, each peripheral will need a separate CS line. To talk to a particular...
Serial Peripheral Interface (SPI) is a four-wire bus. It consists of a serial clock, master output/slave input, master input/slave output, and a device select pin. The speed of the bus range is much higher than that found in I2C or SMBus; speeds up to 80 MHz are not uncommon. Ther...
8 - GPIOs linked to CAPSENSE™ buttons • JTAG interface: JTAG master for code flashing at 400 kHz • General-purpose input/output (GPIO) pins: 17 • Supports unique serial number feature for each device, which fixes ...
SPI Overview The SPI is a four-pin interface with Chip Select (CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. The SPI is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. A ...