Hasan, and S. Hossain, "On the design and analysis of quaternary serial and parallel adders," in Proc. IEEE Region 10 Conference, 2010, p. 1691.Das, A.; Jahangir, I.; Hasan, M.; Hossain, S.; "On the design and analysis of quaternary serial and parallel adders", Proceedings, ...
We shall present and analyze a series of CMOS-based examples for addition starting from the device level and moving up to the gate, the circuit, and the block level. Our analysis, backed by simulation results, on comparing parallel and serial addition shows that serial adders are more ...
The main difference between serial and parallel arithmetic, which is of interest here, is that a shift operation in serial arithmetic require a flip-flop, while it can be hardwired in parallel arithmetic.The possible ways to connect a certain number of adders is limited, i.e., for single-...
Using parallel processing and serial, two's-complement arithmetic, the required arithmetic circuits (adders and multipliers) are quite simple, as are the remaining circuits, which consist of shift registers for delay and small read-only memories for coefficient storage. The arithmetic circuits are ...
registers for storing a row of matrix, comparison register, multipliers, adders, storage registers, output realization storage register.;EFFECT: extraction of useful component under conditions of insufficient a priori information about statistical characteristics of additive noise and useful component function...
PCM communications system encoder - using modulo two adders and parallel:serial converter, for additive or multiplicative codingPCM communications system encoder - using modulo two adders and parallel:serial converter, for additive or multiplicative codingThe PCM communications system allows high-bit-rate ...
A set of designs are derived from the radix-2design procedure, which was first reported by the authors for the design of bit level pipelined digit serial–parallel structures. One significant aspect of the new designs is that they can be pipelined to the bit level and give the designer the...
parallel with all other bit serial processors. Machines based on this approach are known by various names, such as single instruction, multiple data or SIMD machines, parallel processors, and systolic processors. They are typically comprised of an array of identical bit serial processors or "cells...
An efficient fault-tolerant architecture for use in serial-parallel multipliers is proposed. This architecture uses a time redundancy method together with the technique of a fast serial-parallel multiplier to achieve both error detection and error location with small time and hardware overheads. The de...
1. A parallel data processor comprising: first means for generating control signals and address data; and a plurality of substantially identical processing cell means, for processing data one bit at a time, each of the cell means being connected to at least two other cell means, and each of...