This multiplier has an 8-bit bi-directional I/O for inputting its A and B operands, and outputting its 16-bit output one byte at a time. The multiplexed bi-directorial data-bus is used to reduce the total number of pins of the multiplier. Verilog code is used for entire design of ...
The proposed decimal multiplier uses internally a redundant BCD (Binary Coded Decimal) code. The overloaded BCD or ODDS (Overloaded Decimal Digit Set) representation was proposed to improve the decimal Multi-operand addition, sequential and... A Anusha,C. Kumar 被引量: 1发表: 2015年 Modeling of...