Open Vivado and create a new project. Write the Verilog Code for Sequence Detector (Moore and Mealy FSM): Design two Verilog modules: one for a Moore FSM and another for a Mealy FSM to detect a sequence such as
Sequence Detector MealyAIM:Design a controller that detects the overlapping sequence “0X01” in a bit stream using mealy machine.DESIGN Verilog Program- Sequence Detector 0x01 Mealy implementation `timescale 1ns / 1ps /// // Company: TMP // Create Date: 08:15:45 01/12/2015 // Module ...
In this blog I will be implementing a 4-bit sequence detector to simplify the process of the creating the state diagram.The module can be configured to match the state machine parameters using the verilog parameters, we will also be using switch-cases to...