So, if I build (without today commit on litedram/litedram/frontend/wishbone.py as it fails on assertion assert wishbone.addressing == "byte" ), with options: I still can see sdram init failed, but, when I manually read-write upto 4-byte words, it works well: Initializing SDRAM @0x400...
LOG_E("malloc failed"); } } MSH_CMD_EXPORT(sram_test, sram test) 编译烧写后我们使用定义的 sram_test 命令来进行内存堆的申请测试,测试结果如下。根据测试的日志信息我们可以看出系统复位后内存堆的空间为 183400 字节,我们设定的是每次申请 50KB = 51200 字节的空间,每次申请后打印出剩余的内存堆...
(sdram_address_list[section]+i) = i; } for(int i = 0; i < 8192*512; i+=512) { if(i != *(uint32_t *)(sdram_address_list[section] + i)) { result = 1; break; } } } if( result ) { printf("SDRAM test failed!\r\n"); } else { printf("SDRAM test success!\r\n"...
While the system boots up, the memory test failed. Our memory is in x16 configuration but the current code seems to test memory in x8 configuration. I have attached the debug log for reference. Please let us know if any specific changes are required in MRC or in SPD to detect the memory...
1.1 SDRAM数据存储基本原理 板子上的SDRAM型号为：MT48LC16M16A2P-6AIT，它的原理图如下：每个引脚的...
But very sadly, after several weeks debugging, my SDRAM writing/reading test is still not successful. Over the all 64Mbyte space, data bit 1~15 are always OK, only bit0 is 0 for ever. Just like DATA0 line doesn't exist. I've checked the hardware line of DATA0, which is PC00 (...
{right=0; printf("sdram test failed at %d",i); break; } } if (right) printf("sdram test ok!\n"); return 0; } 22. 配置编译器参数为 -Os 。 23. 置 System Library Properties,去掉 Support C++,勾上 Small C library,确认右 边使用的是 onchip_mem,没有使用两块 SDRAM,输入输出使用 jt...
(testing sdram... \n); for (i=0;i0x1000000;i++) *(sdram+i)=0x55aa; right=1; for(i=0;i0x1000000;i++) { temp=*(sdram+i); if (temp!=0x55aa) {right=0; printf(sdram test failed at %d,i); break; } } if (right) printf(sdram test ok!\n); return 0; } 配置编译器...
56//57//Test configured DLY value and find out min./max. values that will work58//59if(_TestSDRAM() ==0) {60//61//Test passed, remember min. DLY value if not done yet62//63if(Min ==0xFF) {64Min =Delay;65}66}else{67//68//Test failed, if a min. value has been found ...
将sdram_top的形参变为wr_add和rd_add编译后运行无问题;再将读的初始地址修改为23d2,读的长度修改为9d253(理论上前面从0003h开始读,最后只读到00feh),发现读信号没有了,原因应该为sdram_cmd的sdram burst配置方式仍然是读出256个,虽然在sdram_test中配置了rd_length是253,但是二者产生了冲突;尝试读初始地址改...