所述取样及保持系统更包括一取样及保持开关,其与该第二源极随耦器的一输出连接. The sample and hold system further includes a sample and hold switch, with its pole is connected to an output coupled to the second source.E·巴赫S·赛勒斯安...
The subject invention is a sample-and-hold circuit that provides current gain and that is suitable for construction according to LSI (large scale integration) techniques. The circuit incorporates a bipolar transistor biased on (in the sample mode) to a predetermined quiescent state. A capacitor is...
Sample and Hold 模拟集成电路设计
The subject invention is a sample-and-hold circuit that provides current gain and that is suitable for construction according to LSI (large scale integration) techniques. The circuit incorporates a bipolar transistor biased on (in the sample mode) to a predetermined quiescent state. A capacitor is...
必应词典为您提供sample-and-hold-circuit的释义,un. 取样维持电路;抽样保持电路; 网络释义: 采样和保持电路;采样保持电路;取样电路;
Designing of a 12-bit 60MS/s sample-and-hold circuit This paper first discusses using a gain-boosted circuit to design a CMOS fully differential sample-and-hold circuit which is used in the high-speed and hig... RQ Liu,XX Jing,XH Wang - 《Journal of Guilin University of Electronic Tech...
This paper first discusses using a gain-boosted circuit to design a CMOS fully differential sample-and-hold circuit which is used in the high-speed and hig... RQ Liu,XX Jing,XH Wang - 《Journal of Guilin University of Electronic Technology》 被引量: 9发表: 2007年 Sample-and-hold circuit...
Moreover, an input FM signal is fed to a sample-and-hold circuit 10 via a frequency voltage converter 4 and sampled and held by a sampling pulse from the gate 9. As a result, a value of a prescribed position of a ripple waveform of the input signal is sampled and the effect of ...
Designing of a 12-bit 60MS/s sample-and-hold circuit This paper first discusses using a gain-boosted circuit to design a CMOS fully differential sample-and-hold circuit which is used in the high-speed and hig... RQ Liu,XX Jing,XH Wang - 《Journal of Guilin University of Electronic Tech...
In a sample-and-hold circuit having two voltage amplifiers (Ai, Ao) connected in series via a swtich (S,), which is arranged to perform on-off operations in accordance with a control signal, the noninverting input terminal of the second voltage amplifier (Ao) of output side is grounded ...