Everything works well except the ENET (phy chip: KSZ8081RNB). We got a very high error / frame rates (around 30-50%)in "ifconfig". Error number is always the same as frame's and it is rx_crc_error. The board takes about 5 mins to get an IP from our router. We checked the...
将TX PHY和RX PHY连接相同的core_rst信号,因此可以保证两个PHY的core_rst同时assert和removal,并且保证了复位有效时间大于40 core_clk cycles。但是这种情况下TX PHY 和 RX PHY的initial都无法完成(init_done和stopstate为0),RX PHY能够接收camera数据,但是出现CRC错误。 ...
4. Where are the CRC errors being reported? By the Xilinx vcu118? Please ensure your Xilinx board is setup properly with all reference clocks being low jitter. It is extremely difficult to debug a PHY using only ping connection in uboot. This is for a number of reasons. 1. Ping requi...
Another phenomenon is that after we have done several deinit and init operations, the CsirxDrv_errorEventIsrFxn() function is not entered, so neither ECC nor CRC increases. At this time, the sensor and serdes have output data, but TDA4...
- if (rxbuf->rxstatus.rs_status & ATH9K_RXERR_CRC) - rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; - if (rxbuf->rxstatus.rs_status & ATH9K_RXERR_PHY) - goto rx_next; - - if (rxbuf->rxstatus.rs_status & ATH9K_RXERR_DECRYPT) { ...
_length_errors rx_over_errors tx_bytes tx_dropped tx_heartbeat_errors multicast rx_crc_errors rx_fifo_errors rx_missed_errors rx_packets tx_carrier_errors tx_errors tx_packets rx_bytes rx_dropped rx_frame_errors rx_nohandler tx_aborted_errors tx_compressed tx_fifo_errors tx_window_errors...
The etherStatsFragments counter tells me the 5 lost packets were too short frames with crc error. How can this happen? I'm not an ethernet guru and I don't know the mac and phy internal processes. Could it be that the part of rx frame data which overlaps with...
Hi, I am trying to interface sony IMX 290 camera with the ZedBoard. Since the 7 series devices do not support MIPI DPHY natively, I designed a PCB with a compatible solution from https://docs.xilinx.com/v/u/en-US/xapp894-d-phy-solutions.
- CRC and ECC generation - Programmable timing parameters MIPI CSI2 Rx 1: MIPI CSI2 Receiver...
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