ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault) RISCV_PTR do_trap_insn_illegal RISCV_PTR do_trap_break RISCV_PTR do_trap_load_misaligned RISCV_PTR do_trap_load_fault RISCV_PTR do_trap_store_misaligned RISCV_PTR do_trap_store_fault RISCV_PTR do_trap_ecall_u/*system call*/RISCV_...
012Instruction page fault 013Load page fault 014Reserved 015Store/AMO page fault 016–23Reserved 024–31Designated for custom use 032–47Reserved 048–63Designated for custom use 0≥64Reserved Supervisor Trap Value (stval) Register 由于scause不足以表示异常发生的所有信息,比如发生了缺页异常,就会将s...
Sstvecdstvec.MODEmustbecapableofholdingthevalue0(Direct).Whenstvec.MODE=Direct,stvec.BASEmustbecapableofholdinganyvalidfour-byte-alignedaddress. Sstvalastvalmustbewrittenwiththefaultingvirtualaddressforload,store,andinstructionpage-fault,access-fault,andmisalignedexceptions,andforbreakpointexceptionsotherthantho...
如果是取指令操作造成的异常为“Instruction access fault”。 如果是Load指令(数据存储器读操作)造成的异常为“Load access fault”。 如果是Store指令(数据存储器写操作)或者AMO(原子操作指令)造成的异常为“Store/AMO access fault”。有关“异常”的详情,请参见第3章。
do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, "Oops - store (or AMO) address misaligned");irqentry_nmi_exit(regs, state); } } #endif DO_ERROR_INFO(do_trap_store_fault, SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault"); DO_ERROR_INFO(do_trap_ecall_u, ...
(0x00000073) ecall core 0: exception trap_user_ecall, epc 0x000000004000f93c core 0: 0x0000000080001c00 (0xee010113) addi sp, sp, -288 core 0: 0x0000000080001c04 (0x00113423) sd ra, 8(sp) core 0: exception trap_store_access_fault, epc 0x0000000080001c04 core 0: tval 0x000000007...
每个RISC-V机器指令的执行都会涉及一或多个内存访问,具体细分为隐式访问(implicit access)和显式访问(explicit access)。每个指令都会涉及一个隐式访存(即获取指令),来获得待执行指令的编码。大多RISC-V指令在取指之后并不会进行更多访存。特别地,Load和Store指令会对指令所确定的地址进行显式的读取或写入。在非特权...
12, 1 First encountered page fault or access fault With physical address for instruction: 1 Instruction access fault 2 Illegal instruction 0 Instruction address misaligned 8, 9, 11 Environment call 3 Environment break 3 Load/store/AMO address breakpoint Optionally: 4, 6 Load/store/AMO address mi...
各种trap发生时向mtval写入的值的含义(如果有)具体见priv spec中相关段落。 If mtval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address...
Kernelvec在保存寄存器后跳转到kerneltrap(kernel/trap.c:134)。 kerneltrap为两种类型的陷阱做好了准备: 设备中断和异常。 它调用devintr(kernel/trap.c:177)来检查和处理前者。 如果陷阱不是设备中断,则必定是一个异常,内核中的异常将是一个致命的错误; ...