<path to llvm build>/bin/llvm-lit --version ###路径可以直接写全路径 2、下载test-suite git clone https://github.com/llvm/llvm-test-suite.git test-suite 3、构建suite,注意路径 cmake -DCMAKE_C_COMPILER=/llvm/rvv-llvm/build/bin/clang -C../test-suite/cmake/caches/O3.cmake ../test-...
这里我们针对LLVM test-suite,里面是完全的程序,是单独的一个仓库,而不是make check所执行的单元测试和回归测试。 测试分为两种: 测试交叉工具链LLVM编译出的程序是否可以在D1上实际运行; riscv native LLVM是否可以成功编译程序并且程序能够正确运行。 测试交叉工具链LLVM编译出的程序是否可以在D1上实际运行 交叉...
$ riscof run --config config.ini --suite riscv-test-suite/ --env riscv-test-suite/env Running the coverage command You can run the coverage using the following command: $ riscof coverage --config=config.ini --cgf-file covergroups/dataset.cgf --cgf-file covergroups/m/rv32im.cgf --...
Test Suite The Dejagnu test suite has been ported to RISC-V. This can be run with a simulator for the elf and linux toolchains. The simulator can be selected by the SIM variable in the Makefile, e.g. SIM=qemu, SIM=gdb, or SIM=spike (experimental).In addition, the simulator can als...
-doc//wujian100_open user guide|--fpga//FPGA script|--lib//compile script for simulation|--regress//regression result|--sdk//software design kit|--soc//Soc RTL source code|--tb//test bench|--tools//simulation script and setup file|--workdir//simulation directory|--LICENSE|--README.md...
Folders and files Latest commit History13 Commits scripts src .gitignore LICENSE NOTICE README.md build.sh Repository files navigation README Apache-2.0 license riscv-brs-tests RISC-V Boot and Runtime Services Test SuiteAbout RISC-V Boot and Runtime Services Test Suite Resources Read...
VEXRISCV_REGRESSION_TEST_ID [Int[,\Int]*] Random configuration that should be keeped and tested VEXRISCV_REGRESSION_CONFIG_COUNT Int Number of random configurations VEXRISCV_REGRESSION_CONFIG_RVC_RATE 0.0-1.0 Chance to generate a RVC config VEXRISCV_REGRESSION_CONFIG_LINUX_RATE 0.0-1.0 Chance...
Generator.scala & RocketTestSuite.scala 这两个文件是测试相关的,所以我不做说明。 第一个看的Scala文件是:TestHarness.scala 带//注释的就是解释。 下图是 TestHarness.scala 生成的连接图。 第二个看的Scala文件是:ExampleRocketSystem.scala 可以知道 TestHarness.scala 就是testbench,而 ExampleRocketSystem.sc...
Efinix's Sapphire SoC suite of RISC-V processors provides a range of choices to meet your design requirements from a tiny soft core (Sapphire Lite SoC) to a highly configurable soft core (Sapphire SoC) to a 1-GHz capable hard core (High-performance Sapphire SoC). The Sapphire SoCs are ...
虽然处理器是一种硬件设计，其主要目标是正确执行软件，软件在整个验证过程中发挥重要作用。本文介绍了有关使用RISC-V处理器合规性套件(compliance suite)、验证测试的最新发展，并且是使用基于参考模型(reference model-based)的处理器DV流程的有用指南。处理器验证不是什么新话题，但由于RISC-V是一个开放...