原文:The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Chapter 1 (Document Version 20191214-draft) November 19, 2021 虽然是翻译但其实本质上还是个人笔记... 所以一切请以最新的官方标准文档为准。其实之前也有大佬翻译过,但是后来版本更新了,所以我想在加深理解RISC-V spec的同时顺便翻译翻译～ ...
可以将这些指令分为两大类:对控制与状态寄存器(CSR, Control and status registers)进行原子读-写-修改(atomically read-modify-write)的指令;以及所有其它潜在的特权指令(privileged instructions)。CSR指令会在Chapter 10中介绍,下面介绍的是基础非特权指令(base unprivileged instructions)。 系统指令的定义允许简单实现...
The RISC-V privileged architecture covers all aspects of RISC-V systems beyond the unprivileged ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices. Each privilege level has a core set of privileged ISA extensions...
RiscV官方文档规范:https://riscv.org/specifications/ Risc-V文档包括:非特权指令集架构(最早称作用户层指令集架构)文档和特权指令集架构文档,下面这两个文件的官网链接。 Unprivileged ISA Specification Privileged ISA Specification 一些有用的文档,论坛和开源rtl实施链接: 蜂鸟e203 riscv:https://github.com/SI-R...
RsrvNonEventual indicates that the operations are supported (the location is reservable), but without the eventual success guarantee described in the unprivileged ISA specification. RsrvEventual indicates that the operations are supported and provide the eventual success guarantee. We recommend providing ...
These instructions are defined in the Unprivileged Spec, but fall into a category of instructions that use theSYSTEMopcode, indicating that they may require privileged access to execute successfully. The only otherSYSTEMinstructions that are defined in the Unprivileged Spec fall under theZicsrextension...
For more details, please seeThe RISC-V ISA Specification, Volume I: Unprivileged Spec march RISC-V ISA strings are defined by appending the supported extensions to the base ISA in the order listed above. For example, the RISC-V ISA with 32, 32-bit integer registers and the instructions to...
The RISC-V unprivileged specification defines four different types of traps at runtime: Contained: the trap is visible to, and handled by, software running inside the execution environment. Requested: the trap is a synchronous exception that is an explicit call to the execution environment requestin...
RV64IisthemandatorybaseISAforRVA23U64andislittle-endian.Aspertheunprivilegedarchitecturespecification,theecallinstructioncausesarequestedtraptotheexecutionenvironment. RVA23U64MandatoryExtensions ThefollowingmandatoryextensionswerepresentinRVA22U64. MIntegermultiplicationanddivision. ...
These can be divided into two main classes: those that atomically read-modify-write control and status registers (CSRs), and all other potentially privileged instructions. CSR instructions are described in [csrinsts], and the base unprivileged instructions are described in the following section....