We briefly note that the entire privileged-level design described in this document could be replaced with an entirely different privileged-level design without changing the unprivileged ISA, and possibly without even changing the ABI. In particular, this privileged specification was designed to run exis...
I'm trying to add support for specifying a spec version to the Sail model, but I'm having a really hard time working out which versions of the specs actually exist. As far as I can tell there's RISC-V Technical Specificationshas the latest versions, Unpriv 20240411 and Priv 20240411 RI...
RVA23S64 has ten unprivileged options (Zvkng, Zvksg, Zacas, Zvbc, Zfh, Zbc, Zvfh, Zfbfmin, Zvfbfmin, Zvfbfwma) from RVA23U64, and six privileged options (Sv48, Sv57, Svadu, Zkr, Sdext, Ssstrict). Localized Options There are no privileged localized options in RVA23S64 Developmen...
RVA23S64hastenunprivilegedoptions(Zvkng,Zvksg,Zacas,Zvbc,Zfh,Zbc,Zvfh,Zfbfmin,Zvfbfmin,Zvfbfwma)fromRVA23U64,andsixprivilegedoptions(Sv48,Sv57,Svadu,Zkr,Sdext,Ssstrict). LocalizedOptions TherearenoprivilegedlocalizedoptionsinRVA23S64 DevelopmentOptions TherearenoprivilegeddevelopmentoptionsinRVA23S64...
Supporting substantial extensions is one of the primary goals of RISC-V, and hence we define a standard interface to allow unchanged privileged-mode code, particularly a supervisor-level OS, to support arbitrary user-mode state extensions. To date, the V extension is the only standard extension ...
riscv-privileged.adoc riscv-unprivileged.adoc rnmi.adoc rv-32-64g.adoc rv32.adoc rv32e.adoc rv64.adoc rvwmo.adoc scalar-crypto.adoc smcdeleg.adoc smcntrpmf.adoc smctr.adoc smdbltrp.adoc smepmp.adoc smstateen.adoc sscofpmf.adoc ssdbltrp.adoc sstc.adoc supervisor.adoc svgnam.de...
In our post onCaller and Callee Saved Registers, we introduced 32General Purpose Registers (GPRs)defined in the RISC-V ISA. These registers are defined in the Unprivileged Spec and are sometimes referred to asinteger registers. The RISC-V Privileged Spec defines additional registers referred to as...
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interaction with privileged architectures 1. Introduction This document describes the draft of the RISC-V base vector extension. The document describes all the individual features of the base vector extension. Note This is a draft of a stable proposal for the vector specification to be used for ...
The RISC-V privileged architecture provides fields inmisato control theunprivilegedISA at each level to support emulating different base ISAs on the same hardware. we divide each RISC-V instruction-set encoding space (and related encoding spaces such as the CSRs) into three disjoint categories: ...