The single event upset resistant resettable D flip-flop disclosed by the invention has strong single event upset resistance, is suitable for a standard cell library of a single event upset resistance reinforced integrated circuit, and is applied to the fields of aviation, aerospace and the like....
In Section 3, a new Edge Triggered Resettable D-Flip Flop Structure is proposed. Section 4 addresses QCA implementation, simulation results and discussions. Section 5 concludes this paper. Access through your organization Check access to the full text by signing in through your organization. ...
even in the presence of a valid NVMWR signal. If the NVMWR is externally activated without the presence of an address strobe AS signal the flip-flop 462 is caused to change state whenever AS is next enabled causing OR gate 446 to go active. If the OR gate 446 goes active the state ...
1464842 Bi-stable circuits HUGHES AIRCRAFT CO 9 Jan 1975 [10 Jan 1974] 955/75 Heading H3T A bi-stable circuit comprises a gate 20, a first inverter 22, a switch 26 and two further inverters 28, 30 connected in cascade, a switch 16 connected from the output of inverter 22 to one ...
RESETTABLE TOGGLE FLIP-FLOP1464842 Bi-stable circuits HUGHES AIRCRAFT CO 9 Jan 1975 [10 Jan 1974] 955/75 Heading H3T A bi-stable circuit comprises a gate 20, a first inverter 22, a switch 26 and two further inverters 28, 30 connected in cascade, a switch 16 connected from the output ...
The scan structure D flip-flop disclosed by the invention has strong single event upset resistance, is suitable for a standard cell library of a single event upset resistance reinforced integrated circuit, and is applied to the fields of aviation, aerospace and the like....
so that the counters do not overflow. To stop the propagation of the oscillation signal through ring oscillator1905, StopL signal1909is set LOW, RS flip-flop1908is reset, and ring oscillator1905is returned to the STATIC mode of operation. Also, the data in counters1930-1937are isolated from...
The resettable monostable flip-flop circuit has the input signal line (a) coupled to the input of a first gate (5), to the input of a second gate (4) and over an inverter (3) to the input of a second monoflop ((2). The first gate output is connected to th input of a first ...
To achieve high information-processing density, moreover, a ternary flip-flap-flop gate is realized in the molecular logic because the fact that this photochromic molecule can be photoswitched anywhere in its UV-vis spectrum enabled three different lasers (532, 473, and 561 nm) as the inputs...
The designed D flip-flop uses 95 cells for implementation and will function properly in one period of time.doi:10.1016/j.micpro.2018.06.006Saeid ZokaMohammad GholamiMicroprocessors and MicrosystemsZoka, S., Gholami, M.: A novel rising Edge triggered resetta- ble D flip-flop using five input...