eg: #define I2C_SCL(bit) \ if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL I2C_DELAY This delay is invoked four times per clock cycle so this controls the rate of data transfer. The data rate thus ...
INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has...
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL I2C_DELAY This delay is invoked four times per clock cycle so this controls the rate of data transfer. The data rate thus is 1 / (I2C_DELAY * 4). Often defined to be something like...
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL I2C_DELAY This delay is invoked four times per clock cycle so this controls the rate of data transfer. The data rate thus is 1 / (I2C_DELAY * 4). Often defined to be something like...
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL I2C_DELAY This delay is invoked four times per clock cycle so this controls the rate of data transfer. The data rate thus is 1 / (I2C_DELAY * 4). Often defined to be something like...
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL I2C_DELAY This delay is invoked four times per clock cycle so this controls the rate of data transfer. The data rate thus is 1 / (I2C_DELAY * 4). Often defined to be something like...
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL I2C_DELAY This delay is invoked four times per clock cycle so this controls the rate of data transfer. The data rate thus is 1 / (I2C_DELAY * 4). Often defined to be something like...