RCC->PLLSAICFGR = 0x24003000; #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; /* Disable Timers cloc...
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RCC->PLLSAICFGR = 0x24003000; #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; /* Disable Timers cloc...
RCC->CR&= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */ RCC->DCKCFGR = 0x00000000; #if defined(STM32F410xx) /* Disable LPTIM and FMPI2C clock prescalers selecti...