2.定义宏: 3.注意salve interface中有两个hready信号,其中一个hready是slave自己发出的,而hready_in则是slave要接收的(协议里面的interconnect给的,interconnect也会发送此signal给master),在原始方法中hready_bus最中会赋值给slave的hready_in和master的hready。这里由于没有使用ahb bus所以需要自己给slave的hready_in赋...
super.new (name, parent);endfunctionral_sys_trafficm_ral_model;//Register Modelreg2apb_adapterm_reg2apb;//Convert Reg Tx <-> Bus-type packetsuvm_reg_predictor#(bus_pkt) m_apb2reg_predictor;//Map APB tx to register in modelmy_agentm_agent;//Agent to drive/monitor transactionsvirtualfu...
This is why we have a UVM Register Abstraction Layer (UVM-RAL). It attempts to mirror the values of the design registers in the testbench, so you can easily use the register model to access those registers. The RAL, being at a higher level of abstraction, does not need to know what ...