A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a
In this paper, a new 1 V rail-to-rail comparator is presented with low noise, high speed and low power consumption. We utilize current mirrors to overcome the kickback noise. A new adaptive power control (APC) technique is also proposed to minimize the power dissipation of the comparator....
A high-speed rail-to-rail comparator is described. The comparator has two PMOS transistors, two NMOS transistors, a current source and two voltage-dropped components. A first PMOS transistor has a source terminal coupled to a first voltage source and a gate terminal and a drain terminal coupled...
IEEE Midwest Symposium on Circuits and Systems, v.1S. Park, E. W. Greeneich, and T. A. DeMassa, "Low-power transistor- string and new rail-to-rail comparator in A/D converter," in Proc. 42nd Midwest Symp. Circuits Syst., vol. 1. Aug. 1999, pp. 194-197....
The ADC uses a bootstrapped sampling switch to achieve better linearity and also adopts a generalized non-binary redundant algorithm and a rail-to-rail dynamic latched comparator to obtain higher Effective Number of Bits (ENOB). This ADC designed and fabricated in 0.18μm CMOS process achieves a...
rail-to-rail amplifying circuit in the technical field of integrated circuits, which comprises NMOS transistors with normal threshold, such as MN1, MN2, MIN, MAN1, MAN2 and MLN1 to MLN7, and PMOS transistors with normal threshold, such as MP1, MP2, MIP, MAP1, MAP2 and MLP1 to MLP...
8 Chapter 2 Theory of Basic CMOS Comparator Design 2.1. CMOS COMPARATOR CHARACTERIZATION :- A positive voltage ...2) RAIL –TO-RAIL OUTPUT: As in most of the other designs of the latches, there is always a biasing ... D Parida 被引量: 0发表: 1980年 A Novel High Performance CMOS Ca...
A novel ultra low-voltage/low-power rail-to-rail comparator topology in nanoscale CMOS technology The article addresses a novel topology of analog voltage comparator capable of processing the input voltage in rail-to-rail range. We propose two different... L Nagy,M Potocn,R Ondica,... - ...
A 250KS/s, 0.8V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator A low voltage low power successive approximation register (SAR) analog-to-digital converter (ADC) based on a novel rail-to-rail comparator is proposed in t... SB Kobenge,H Yang ...
This work describes a simple topology for implementing a low voltage rail-to-rail CMOS Miller OTA with differential pair using bulk driven and DC shifters... LHDC Ferreira,TC Pimenta - IEEE Xplore 被引量: 7发表: 2005年 Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Techno...