Error "Received Illegal Vector" Lost DR6 May Contain Incorrect Information When the First Instruction After a MOV SS, r/m or POP SS is a Store Uncorrectable Error Logged In IA32_CR_MC2_STATUS Results In System Hang IA32_PERF_GLOBAL_CTRL MSR May be Incorrectly Initialized ECC Errors Cannot ...
Due to this erratum, software may be able to see the three-strike logged in the MC3_STATUS (MSR 40Dh, MCACOD = 400h [bits 15:0]) even when MISC_FEATURE_CONTROL.DISABLE_THREE_STRIKE_CNT i...
Error "Received Illegal Vector" May be Lost DR6 May Contain Incorrect Information When the First Instruction After a MOV SS,r/ m or POP SS is a Store An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang IA32_PERF_GLOBAL_CTRL MSR May be ...
a Floating Point Exception APIC Error "Received Illegal Vector" May be Lost An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set Changing the Memory Type for an In-Use P...
Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is Followed by a Stor...
Included in this family of processors is an integrated memory controller (IMC) and integrated I/O (IIO) (such as PCI Express* and DMI2) on a single silicon die. This single die solution is known as a monolithic processor. Figure 1-1 and Figure 1-2, shows the processor 2-s...
Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register. 1: Unsupported Request detected at the device/port. These unsupported requests are NP requests inbound that the root port or DMI port received and it detected them as...
DMI2 and the internal devices in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0. 1.1.1 Processor IIO Devices (CPUBUSNO (0)) The processor IIO contains PCI...
DMI2 and the internal devices in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0. Processor IIO Devices (CPUBUSNO (0)) The processor IIO contains PCI devices ...
The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated When The UC Bit is Set After a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H), corrected errors will continue to be counted in the lower 14 bits (bits 51:38) of the Corrected Error ...