VHDL总结（1）——Component, Package, Function 和 Procedure比较1．Component的构架如下：LIBRARY ieee;USE ieee.std_logic_1164.all;Entity component_name IS (declarations)END component_name ARCHITECTURE architecture_name OF component_name IS (COMPONENT, FUNCTION and PROCEDURE descriptions)BEGIN END ...
VHDL之wait 和function、Procedure的用法1.--在VHDL中,wait untilclk='1' 可替代clk'eventandclk='1'做上升沿, --wait untilclk='0' 可以替代clk'eventandclk='1'做下降沿。具体用法如下: --74hc161功能芯片的VHDL程序: Libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; ...