right-hand expression shall be evaluated before the delay,instead of after the delay . 2. the intra-assignment delay and event control can be applied to bothblocking assignments and nonblocking assignments.(此条Verilog标准讲的不是很细,有些模糊) 3.the number of occurrences of an event can be ...
Procedural Assignment DefinitionAn assignment in an Always Construct in a Verilog Design File (.v) that places a value on a Verilog HDL register or an integer. A Procedural Assignment can either be blocking or non blocking. See "Section 9.2: Procedural assignments" in the IEEE Std 1364-2001...