TECHNOLOGY 2E 15 -1 TERA BITS PER SECOND (TBPS) PRBS HDL ASIC...
RTL Design Architecture Implemented by using VHDL &/ Verilog HDL, Programming & Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O.E. Dept...