The clocking wizard receives a 250 MHz differential input and outputs a 20 MHz clock. The clocks are constrained from there, and the timing analysis doesn't show any problems. When running a post-implementation
Hi, I design a module for rgbtogrey. When i start post implementation timing simulation,I get the following result.(gryodata) Everything was seamless until post implementation timing simulation, but here I came across something like this. I would be very