endmodule Line marked with (i), I want wait just posedge clk before sending outp to output port.However, When I have tried like ; if ( posedge clk ) it gives error while ( clk != 1 ) begin end it gives absurb answer/simulation output.What thing(s) should I put to that line to ...
Pls compare below 4 codes: 1, module reset_gen ( output rst_sync_n , input clk , rst_async_n ); logic rst_s1, rst_s2; always_ff @ (